More and more transistors are being integrated in integrated circuits (ICs) allowing to realize devices that satisfy the demand for powerful and flexible applications. The next generation of ICs is going to comprise transistors having a gate length (L) and a gate width (W) of 50 nm and below. In addition to the ongoing miniaturization of the integrated active—known as scaling—and passive elements, new materials and material compositions are being employed in order to increase the processing speed of the ICs and to Improve performance.
A typical example is the deployment of Silicon-Germanium (SiGe) on Silicon. One concept that was recently announced by IBM is based on strained silicon layers in relaxed SiGe layers. Called strained silicon, this concept stretches the materials, speeding the flow of electrons through transistors to increase the performance and decrease the power consumption in ICs. Fabrication of such devices is difficult. First, the growth of the relaxed buffer layer is, due to the required thickness in the range of a few microns, time consuming. This growth process may generate high defect densities and unfavorably low thermal conductance. Second, the high-quality oxide formation requires elevated temperatures, which in turn cause undesirable plastic strain relaxation and dislocation propagation into the active channel. Furthermore, the integration of p-type and n-type transistors on one common substrate is difficult.
A concept that avoids certain disadvantages of the strained silicon approach is described by O. G. Schmidt and K. Eberl in the paper, Self-Assembled Ge/Si Dots for Faster Field Effect Transistors, Max-Planck-Institut fur Festkbrperforschung, Stuttgart, Germany. The researchers propose to employ so-called buried islands. Nanostructured Ge-dots on silicon can serve as buried islands, for example. When the Ge-dots are grown in the Stranski-Krastanow mode with 3–5 monolayers of Ge, there is a strong misfit induced strain around such Ge-dots in the silicon. The position of the Ge-dots can be influenced by pre-structuring the silicon substrate, n-type and p-type transistors are described that have an increased charge flow. A yet unsolved problem is the alignment of the gate electrode with respect to a buried island. For a transistor having a gate length and gate width of less than 50 nm, the overlay accuracy has to be in the range of 20 nm or below. Certain aspects of the work reported in the paper by O. G. Schmidt and K. Eberl are also covered by the German patent application DE 100 25 264. This patent application is an earlier patent document that was published after the filing date of the present application.
It is an object of the present invention to provide a method for making improved active devices, such a n-type or p-type transistors.
It is an object of the present invention to provide improved active devices, such as n-type or p-type transistors.
It is an object of the present invention to provide a method for contacting small transistors or other devices and to provide devices based on this method.